Implementing electronic circuits involves connecting isolated devices or circuit components through specific electronic paths. In silicon integrated circuit (IC) fabrication, it is necessary to isolate devices that are formed in a single substrate from one another. The individual devices or circuit components subsequently are interconnected to create a specific circuit configuration.
As the density of the devices continues to rise, parasitic inter-device currents become more problematic. Isolation technology, therefore, has become an important aspect of integrated circuit fabrication. For example, dynamic random access memory (DRAM) devices generally comprise an array of memory cells for storing data and peripheral circuits for controlling data in the memory cells. Each memory cell in a DRAM stores one bit of data and consists of one transistor and one capacitor. Within the array, each memory cell must be electrically isolated from adjacent memory cells. The degree to which large numbers of memory cells can be integrated into a single IC chip depends, among other things, on the degree of isolation between the memory cells. Similarly, in metal-oxide-semiconductor (MOS) technology, isolation must be provided between adjacent devices, such as NMOS or PMOS transistors or CMOS circuits, to prevent parasitic channel formation.
Shallow trench isolation (STI) is one technique which can be used to isolate devices such as memory cells or transistors from one another. The typical STI process consists of a blanket pad ox, blanket silicon nitride followed by a trench mask and etch through silicon nitride, pad ox and into the crystalline silicon substrate. The mask is stripped and a liner oxide is grown and annealed. Next, high density plasma (HDP) oxide is deposited to fill the trench and again heated to density the deposited oxide. Finally, the HDP oxide overburden is polished back to the buried silicon nitride and the silicon nitride/pad oxide is stripped prior to gate oxidation. As the HDP fills the trench it forms a vertical seam where the deposited layers of the HDP begin to join to fill the trench.
During the high temperature processing at liner oxide anneal and HDP oxide densification, stresses can develop because of non-uniform heating of the wafer. Within the active region, these stresses can modify the transistor performance. At the wafer level, non-uniformity of stress can cause localized overlay registration errors during the gate masking process. In addition, during the mechanical planarization this seam of the HDP is more vulnerable to over etching as compared to the adjacent HDP layer. As a result, a defect can be created at the seam that can lead to operational problems for the device.
Accordingly, it is desirable to improve the trench isolation techniques to address those and similar problems.